1. Field of the Invention
The present invention relates to a converter, and in particular, to a converter that converts serial data to parallel data and parallel data to serial data.
2. Background of the Related Art
As shown in FIG. 1, a related art serial to parallel converter includes serial transmitting latches STL1-STL4 that are synchronized by receiving a serial clock signal SCLK. Parallel transmitting latches PTL1-PTL4 are initialized and synchronized by receiving a initialization signal SB and a parallel clock signal PCLK, respectively.
The operation of the related art serial to parallel converter will now be described assuming a 4 bit input data signal ID. As shown in FIG. 2C, the input data signal is serially input to a first serial transmitting latch STL1 at every rising edge of the serial clock signal SCLK, which is shown in FIG. 2A. A data signal output from the serial transmitting latch STL1 is inputted to a second serial transmitting latch STL2 at a next rising edge of the serial clock signal SCLK. The above process is repeatedly performed to transmit the input data signal ID (e.g., the 4 bit input data) to each of the serial transmitting latches STL1-STL4. That is, the input data signal ID of 4 bits is received by each of the serial transmitting latches STL1-STL4 after 4 rising edges of the serial clock signal SCLK.
Each of the parallel transmitting latches PTL1-PTL4 respectively receives the serial input data signal ID, which was received by each of the serial transmitting latches STL1-STL4, and outputs in parallel output data OD0-OD3 as shown in FIGS. 2D to 2G at a rising edge of the parallel clock signal PCLK. The parallel clock signal is shown in FIG. 2B.
An initial output value of cells of each of the parallel transmitting latches PTL1-PTL4 is maintained at a high level in accordance with the initialization signal SB as shown in FIG. 2H. The parallel transmitting latches PTL1-PTL4 output the serial input data signal ID at a normal state as the parallel output data OD0-OD3 after the rising edge of the parallel clock signal PCLK.
However, the related art serial to parallel converter has various disadvantages. The related art converter converts the serial input data to the parallel data, but is not able to convert the parallel data to the serial data.